The present disclosure relates generally to the field of fabrication of semiconductor devices, and more specifically to a method of fabricating a fin type field effect transistor (FinFET).
Double-gate MOSFETs are MOSFETs that incorporate two gates into a single device. These devices are also known as FinFETs due to their structure including a thin “fin,” extending from a substrate. FinFETs may be fabricated using conventional MOSFET technology. A typical FinFET is fabricated on a silicon layer with an overlying insulating layer and the device extends from the insulating layer as a fin of silicon. The channel of the FET is formed in this vertical fin. A double gate is provided over the fin. The double gate is beneficial in that there is a gate on both sides of the channel allowing gate control of the channel from both sides. Further advantages of FinFETs include reducing the short channel effect and higher current flow. Other FinFET architectures may include three or more effective gates.
Current FinFET technology has challenges however. For example, ion implantation is typically used to form a lightly doped drain (LDD). Ion implantation creates a non-conformal doping profile of the fin (for example, heavier doping at the top of the fin than the bottom of the fin, which is found closer to the substrate) however. This non-conformal doping profile may create issues including those associated with short channel effects. By using a tilt implant, the uniformity may be improved, but shadowing effects will be disadvantageous. Plasma immersion ion implantation has an ion energy such that it may be too low to satisfy FinFET device performance requirements.
As such, an improved fabrication method for a FinFET element is desired.